AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 623

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.7.16
Name:
Access Type:
Offset:
Reset Value:
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32072C–AVR32–2010/03
PDCM: Peripheral DMA Controller Mode
DLC: Data Length Control
WKUPTYP: Wakeup Signal Type
FSDIS: Frame Slot Mode Disable
DLM: Data Length Mode
CHKTYP: Checksum Type
CHKDIS: Checksum Disable
PARDIS: Parity Disable
WKUPTYP
31
23
15
–
–
7
0: The LIN mode register LINMR is not written by the Peripheral DMA Controller.
1: The LIN mode register LINMR (excepting that bit) is written by the Peripheral DMA Controller.
0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes.
0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal.
1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal.
0: The Frame Slot Mode is enabled.
1: The Frame Slot Mode is disabled.
0: The response data length is defined by the field DLC of this register.
1: The response data length is defined by the bits 4 and 5 of the Identifier (IDCHR in LINIR).
0: LIN 2.0 “Enhanced” Checksum
1: LIN 1.3 “Classic” Checksum
0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum
is checked automatically.
1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked.
0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node
configuration, the parity is checked automatically.
1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.
LIN Mode Register
FSDIS
30
22
14
LINMR
Read-write
0x54
0x00000000
–
–
6
DLM
29
21
13
–
–
5
CHKTYP
28
20
12
–
–
4
DLC
CHKDIS
27
19
11
–
–
3
PARDIS
26
18
10
–
–
2
AT32UC3A3/A4
25
17
–
–
9
1
NACT
PDCM
24
16
–
8
0
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