AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 555
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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25.6.3.3
32072C–AVR32–2010/03
Asynchronous Receiver
Figure 25-9. Start Frame Delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system
allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be
set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as nor-
mal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles
before the expected edge, then the current period is shortened by one clock cycle. If the RXD
event is between 2 and 3 clock cycles after the expected edge, then the current period is length-
ened by one clock cycle. These intervals are considered to be drift and so corrective actions are
automatically taken.
Figure 25-10. Bit Resynchronization
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (MR).
Oversampling
Sampling
16x Clock
point
RXD
Manchester
Manchester
Manchester
encoded
encoded
encoded
data
data
data
Preamble Length
Synchro.
Txd
Txd
Txd
Error
is set to 0
Synchro.
SFD
SFD
SFD
Jump
DATA
One bit start frame delimiter
Expected edge
Tolerance
start frame delimiter
start frame delimiter
DATA
DATA
Command Sync
Jump
Sync
AT32UC3A3/A4
Data Sync
Synchro.
Error
555
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