AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 323
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 323 of 1014
- Download datasheet (16Mb)
19.9.1
19.9.1.1
Figure 19-7. Multi-block Transfer Using Linked Lists
32072C–AVR32–2010/03
Multi-block Transfers
LLPx(0)
Block Chaining Using Linked Lists
CTLx[63..32]
CTLx[31..0]
LLPx(1)
DARx
SARx
A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These regis-
ters, along with the CFGx register, are used by the DMACA to set up and describe the block
transfer.
In this case, the DMACA re-programs the channel registers prior to the start of each block by
fetching the block descriptor for that block from system memory. This is known as an LLI update.
DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the
address in memory of the next linked list item. Each LLI (block descriptor) contains the corre-
sponding block descriptor (SARx, DARx, LLPx, CTLx).
To set up block chaining, a sequence of linked lists must be programmed in memory.
The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update.
The updated contents of the CTLx register are written back to memory on block completion.
ure 19-7 on page 323
transfers using block chaining.
The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base
address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN.
LLI(0)
shows how to use chained linked lists in memory to define multi-block
System Memory
LLPx(1)
CTLx[63..32]
CTLx[31..0]
LLPx(2)
DARx
SARx
LLI(1)
AT32UC3A3/A4
LLPx(2)
Fig-
323
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