AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 814

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29. HSB Bus Performance Monitor (BUSMON)
29.1
29.2
29.3
32072C–AVR32–2010/03
Features
Overview
Block Diagram
Rev 1.0.0.0
•
•
•
BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
Up to 4 device-specific masters can be measured. Each of these masters is part of a measure-
ment channel. Which masters that are connected to a channel is device-specific. Devices may
choose not to implement all channels.
Figure 29-1. BUSMON Block Diagram
Allows performance monitoring of High Speed Bus master interfaces
The following is monitored
Automatic handling of event overflow
– Up to 4 masters can be monitored
– Peripheral Bus access to monitor registers
– Data transfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
Master A
Master B
Master C
Master D
Master E
Master F
Master G
Master H
Master I
Master J
Master K
Master L
Master M
Master N
Master O
Master P
Channel 0
Channel 1
Channel 2
Channel 3
Registers
Registers
Registers
Registers
Control
Peripheral Bus Interface
Slave 0
Slave 1
Slave 2
Slave 3
AT32UC3A3/A4
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