AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 66

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6.10
Name:
Access Type:
Offset:
Reset Value:
• BOD33DET: Brown out detection
• BODDET: Brown out detection
• OSC32RDY: 32 KHz oscillator Ready
• OSC1RDY: Oscillator 1 Ready
• OSC0RDY: Oscillator 0 Ready
• MSKRDY: Mask Ready
• CKRDY: Clock Ready
32072C–AVR32–2010/03
OSC0RDY
31
23
15
7
-
-
-
This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected:
going below BOD33 reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected:
below BOD reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected:
ready to be used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected:
(CPU/HSB/PBA/PBB)_MASK registers.
This bit is cleared when the corresponding bit in ICR is written to one.
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing a one to ICR.CKRDY has no effect.
Interrupt Status Register
MSKRDY
30
22
14
6
-
-
-
ISR
Read-only
0x4C
0x00000000
CKRDY
29
21
13
5
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
BOD has detected that power supply is going
BOD33 has detected that power supply is
Oscillator 1 is stable and ready to be used
Oscillator 1 is stable and ready to be used
Clocks are now masked according to the
26
18
10
2
-
-
-
-
The 32 KHz oscillator is stable and
OSC32RDY
BOD33DET
AT32UC3A3/A4
LOCK1
25
17
9
1
-
OSC1RDY
BODDET
LOCK0
24
16
8
0
-
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