AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 815

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29.4
29.4.1
29.5
32072C–AVR32–2010/03
Product Dependencies
Functional Description
Clocks
In order to use this module, other parts of the system must be configured correctly, as described
below.
The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager.
This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to
disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined
state.
Three different parameters can be measured by each channel:
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load and maximum bus latency.
Each of the counters have a fixed width, and may therefore overflow. When overflow is encoun-
tered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles
(STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if
the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit
is written to one, the channel registers are frozen when either DATAn or STALLn reaches its
maximum value. This simplifies one-shot readout of the counter values.
The registers can also be manually reset by writing to the CONTROL register. The Channeln
Max Initiation Latency (LATn) register is saturating, when its max count is reached, it will be set
to its maximum value. The LATn register is reset whenever DATAn and STALLn are reset.
A counter must manually be enabled by writing to the CONTROL register.
• The number of data transfer cycles since last channel reset
• The number of stall cycles since last channel reset
• The maximum continuous number of stall cycles since last channel reset (This approximates
the max latency in the transfers.)
AT32UC3A3/A4
815