AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 192

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
time
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page
an early read wait state, the write operation could not complete properly.
(NWEHOLD = 0), the feedback of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See
NBS0, NBS1,
A[AD_MSB:2]
(Figure 15-16 on page
A0, A1
CLK_SMC
D[15:0]
NWE
NRD
193). The write operation must end with a NCS rising edge. Without
Write cycle
192).
No hold
Early Read
Wait state
Figure 15-18 on page
No setup
Read cycle
AT32UC3A3/A4
194.
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