AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 528

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.9.6
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Transmit Frame Sync Length High Part
• FSEDGE: Transmit Frame Sync Edge Detection
• FSDEN: Transmit Frame Sync Data Enable
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
32072C–AVR32–2010/03
FSDEN
MSBF
FSEDGE
31
23
15
Others
FSOS
7
-
The four MSB of the FSLEN field.
Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
0
1
2
3
4
5
0
1
Transmit Frame Mode Register
Selected Transmit Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
6
-
-
TFMR
Read/Write
0x1C
0x00000000
FSLENHI
DATDEF
FSOS
29
21
13
5
-
28
20
12
4
-
27
19
11
TX_FRAME_SYNC Pin
3
-
Undefined
Input-only
Output
Output
Output
Output
Output
DATLEN
26
18
10
2
-
FSLEN
DATNB
AT32UC3A3/A4
25
17
9
1
-
FSEDGE
24
16
8
0
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