AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 568

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 25-27. Receiver Behavior when Operating with Hardware Handshaking
32072C–AVR32–2010/03
RXBUFF
Write
RXD
RTS
CR
RXEN = 1
Figure 25-26. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the MODE
field in the Mode Register (MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in
standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as
described below and the level on the CTS pin modifies the behavior of the transmitter as
described below. Using this mode requires using the Peripheral DMA Controller channel for
reception. The transmitter can handle hardware handshaking in any case.
Figure 25-27
pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) com-
ing from the Peripheral DMA Controller channel is high. Normally, the remote device does not
start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled,
the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer
to the Peripheral DMA Controller clears the status bit RXBUFF and, as a result, asserts the pin
RTS low.
Figure 25-28
pin disables the transmitter. If a character is being processing, the transmitter is disabled only
after the completion of the current character and transmission of the next character happens as
soon as the pin CTS falls.
Figure 25-28. Transmitter Behavior when Operating with Hardware Handshaking
shows how the transmitter operates if hardware handshaking is enabled. The CTS
shows how the receiver operates if hardware handshaking is enabled. The RTS
CTS
TXD
USART
TXD
RXD
CTS
RTS
RXD
TXD
RTS
CTS
Remote
Device
AT32UC3A3/A4
RXDIS = 1
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