AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 522

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.9.3
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Receive Period Divider Selection
• STTDLY: Receive Start Delay
• STOP: Receive Stop Selection
32072C–AVR32–2010/03
31
23
15
7
-
This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.
Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive
Sync Data reception.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new
Compare 0.
Receive Clock Mode Register
CKG
30
22
14
6
-
RCMR
Read/Write
0x10
0x00000000
CKI
29
21
13
5
-
STOP
28
20
12
4
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
AT32UC3A3/A4
25
17
9
1
CKS
24
16
8
0
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