AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 155

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.5.2
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32072C–AVR32–2010/03
ARBT: Arbitration Type
FIXED_DEFMSTR: Fixed Default Master
DEFMSTR_TYPE: Default Master Type
SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
31
23
15
–
–
–
7
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
The size of this field depends on the number of masters. This size is log2(number of masters).
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having
accessed it.
This results in not having one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number
that has been written in the FIXED_DEFMSTR field.
This results in not having one cycle latency when the fixed master tries to access the slave again.
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
Slave Configuration Registers
30
22
14
SCFG0...SCFG15
Read/Write
0x40 - 0x7C
0x00000010
–
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
FIXED_DEFMSTR
SLOT_CYCLE
27
19
11
–
–
3
26
18
10
–
–
2
AT32UC3A3/A4
25
17
–
9
–
1
DEFMSTR_TYPE
ARBT
24
16
8
–
0
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