DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 995

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SYSCR—System Control Register
Bit
Initial value
Read/Write
CS2 enable
CS2E
SYSCR
R/W
CS2E
Bit 7
7
0
0
1
FGA20E
HICR
Bit 0
Note: * In the H8S/2138 F-ZTAT A-mask version, the address range is from
IOS enable
IOSE
R/W
0
1
0
1
0
1
6
0
The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) *
CS2 pin function halted
(CS2 fixed high internally)
CS2 pin function selected for P81/CS2 pin
CS2 pin function selected for P90/ECS2 pin
H'(FF)F000 to H'(FF)F7FF.
Interrupt control selection mode 1 and 0
INTM1
INTM1
Bit 5
0
1
R
5
0
INTM0
Bit 4
Description
0
1
0
1
INTM0
R/W
External reset
4
0
control mode
0
1
Interrupt
Reset generated by watchdog timer overflow
Reset generated by an external reset
0
1
2
3
NMI edge select
0
1
XRST
Rev. 4.00 Jun 06, 2006 page 939 of 1004
R
Falling edge
Rising edge
H'FFC4
3
1
Interrupts controlled by I bit
Interrupts controlled by I and UI bits, and ICR
Cannot be used in the LSI
Cannot be used in the LSI
Host interface enable
0
1
NMIEG
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
Appendix B Internal I/O Registers
R/W
2
0
RAM Enable
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
R/W
HIE
1
0
REJ09B0301-0400
RAME
(Initial value)
R/W
0
1
System