DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 585

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.2.3
HICR is an 8-bit readable/writable register which controls host interface interrupts and the fast
A20 gate function. HICR is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Input Data Register Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2
interrupt to the internal CPU.
Bit 1— Input Data Register Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1
interrupt to the internal CPU.
Bit 0
HI12E
0
1
Bit 2
IBFIE2
0
1
Bit 1
IBFIE1
0
1
Bit
Initial value
Slave Read/Write
Host Read/Write
Host Interface Control Register (HICR)
Description
Input data register (IDR2) receive complete interrupt is disabled
Input data register (IDR2) receive complete interrupt is enabled
Description
Input data register (IDR1) receive complete interrupt is disabled
Input data register (IDR1) receive complete interrupt is enabled
Description
Host interface functions are disabled
Host interface functions are enabled
—
—
—
7
1
—
—
—
6
1
—
—
—
5
1
—
—
—
4
1
Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 529 of 1004
—
—
—
3
1
IBFIE2
R/W
—
2
0
IBFIE1
REJ09B0301-0400
R/W
—
1
0
(Initial value)
(Initial value)
(Initial value)
FGA20E
R/W
—
0
0