DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 203
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 203 of 1063
- Download datasheet (6Mb)
16-Bit Access Space (Cannot Be Used in the H8S/2138 Group or H8S/2134 Group): Figure
6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the
upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of
data that can be accessed at one time is one byte or one word, and a longword access is executed
as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
6.4.3
Table 6.5 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
These group only have an upper data bus, and only the RD and HWR signals are valid. In these
group, the HWR signal pin is designated WR.
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
Valid Strobes
Byte size
Byte size
Word size
Longword
size
• Even address
• Odd address
1st bus cycle
2nd bus cycle
D15
Upper data bus
Rev. 4.00 Jun 06, 2006 page 147 of 1004
D8 D7
Lower data bus
Section 6 Bus Controller
REJ09B0301-0400
D0
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