DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 598

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
HIRQ Setting/Clearing Contention: If there is contention between a P4DR read/write by the
CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) clearing by the host, clearing by the host is held
pending during the P4DR read/write by the CPU. P4DR clearing is executed after completion of
the read/write.
17.5
The host interface provides buffering of asynchronous data from the host and slave processors, but
an interface protocol must be followed to implement necessary functions and avoid data
contention. For example, if the host and slave processors try to access the same input or output
data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple
and effective protocol.
Also, if CS1 and CS2 or ECS2 are driven low simultaneously in attempting IDR or ODR access,
signal contention will occur within the chip, and a through-current may result. This usage must
therefore be avoided.
Rev. 4.00 Jun 06, 2006 page 542 of 1004
REJ09B0301-0400
No
No
Usage Note
Write 1 to P4DR
Write to ODR
P4DR = 0?
transferred?
All bytes
Yes
Yes
Figure 17.3 HIRQ Output Flowchart
Slave CPU
HIRQ output high
HIRQ output low
Hardware operations
Software operations
Interrupt initiation
Master CPU
ODR read