DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 952

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
DDCSWR—DDC Switch Register
Rev. 4.00 Jun 06, 2006 page 896 of 1004
REJ09B0301-0400
Notes: 1. Only 0 can be written, to clear the flag.
Bit
Initial value
Read/Write
2. Always read as 1.
DDC mode switch enable
0
1
SWE
R/W
7
0
Automatic switching of IIC channel 0 from formatless mode
to I
Automatic switching of IIC channel 0 from formatless mode
to I
2
2
DDC mode switch
C bus format is disabled
C bus format is enabled
0
1
R/W
IIC channel 0 is used with the I
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
SW
6
0
DDC mode switch interrupt enable bit
0
1
Interrupt when automatic format switching is executed
is disabled
Interrupt when automatic format switching is executed
is enabled
DDC mode switch interrupt flag
R/W
0
1
IE
5
0
No interrupt is requested when automatic
format switching is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
An interrupt is requested when automatic
format switching is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
IIC clear bits
CLR3
Bit 3
0
1
R/(W) *
CLR2
IF
Bit 2
4
0
—
0
1
1
CLR1
Bit 1
—
—
0
1
CLR3
W *
2
3
1
C bus format
CLR0
Bit 0
—
—
2
0
1
0
1
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
H'FEE6
CLR2
W *
2
1
2
CLR1
Description
W *
1
1
2
CLR0
W *
0
1
2
IIC0