DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 147
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 147 of 1063
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4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1
Notes: 1. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
Priority
High
Low
2. Trap instruction exception handling requests are accepted at all times in the program
Exception Handling Types and Priority
Overview
Exception Type
Reset
Trace
Interrupt
Direct transition
Trap instruction (TRAPA) *
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
Section 4 Exception Handling
2
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1.
(Cannot be used with this LSI.)
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued. *
Started by a direct transition resulting from execution of a
SLEEP instruction.
Started by execution of a trap instruction (TRAPA).
Rev. 4.00 Jun 06, 2006 page 91 of 1004
Section 4 Exception Handling
REJ09B0301-0400
1
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