DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 574

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
Rev. 4.00 Jun 06, 2006 page 518 of 1004
REJ09B0301-0400
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
Notes on Interrupt Occurrence after ACKB Reception
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Conditions to cause this failure
The IRIC flag is set to 1 when both of the following conditions are satisfied.
When the above two conditions are satisfied in slave receive mode, an unnecessary
interrupt occurs.
Figure 16.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the
acknowledge bit (ACKB = 1).
(1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received
(2) After switching to slave receive mode, the start condition is input, and address
(3) Even if the received address does not match the address set in SAR or SARX, the IRIC
Note that if the slave address matches, an interrupt is to be generated at the rise of the 9th
transmit/receive clock as normal operation, so this is not erroneous operation.
Restriction
In a transmit operation of the I
countermeasures.
(1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in
(2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again.
1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set
to 1
Rising edge of the 9th transmit/receive clock is input to the SCL pin
as the acknowledge bit.
If the ACKE bit in ICCR is set to 1 at this time, the ACKB bit in ICSR is set to 1.
reception is performed next.
flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to
occur.
ICCR to 0 to clear the ACKB bit to 0.
2
C Bus Interface [H8S/2138 Group Option]
2
C bus interface module, carry out the following