DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 461
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 461 of 1063
- Download datasheet (6Mb)
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
15.2.8
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR
settings in synchronous mode.
Bit 0
MPBT
0
1
Bit
Initial value
Read/Write
Bit Rate Register (BRR)
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
R/W
7
1
R/W
6
1
R/W
5
1
Section 15 Serial Communication Interface (SCI, IrDA)
R/W
4
1
Rev. 4.00 Jun 06, 2006 page 405 of 1004
R/W
3
1
R/W
2
1
R/W
REJ09B0301-0400
1
1
(Initial value)
R/W
0
1
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