DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 25
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 10 14-Bit PWM D/A
10.1 Overview........................................................................................................................... 253
10.2 Register Descriptions ........................................................................................................ 256
10.3 Bus Master Interface ......................................................................................................... 262
10.4 Operation .......................................................................................................................... 265
Section 11 16-Bit Free-Running Timer
11.1 Overview........................................................................................................................... 269
11.2 Register Descriptions ........................................................................................................ 273
11.3 Operation .......................................................................................................................... 287
9.3.1
10.1.1 Features................................................................................................................ 253
10.1.2 Block Diagram ..................................................................................................... 254
10.1.3 Pin Configuration................................................................................................. 255
10.1.4 Register Configuration......................................................................................... 255
10.2.1 PWM D/A Counter (DACNT) ............................................................................. 256
10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 257
10.2.3 PWM D/A Control Register (DACR) .................................................................. 259
10.2.4 Module Stop Control Register (MSTPCR) .......................................................... 261
11.1.1 Features................................................................................................................ 269
11.1.2 Block Diagram ..................................................................................................... 270
11.1.3 Input and Output Pins .......................................................................................... 271
11.1.4 Register Configuration......................................................................................... 272
11.2.1 Free-Running Counter (FRC) .............................................................................. 273
11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 273
11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 274
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 275
11.2.5 Output Compare Register DM (OCRDM) ........................................................... 276
11.2.6 Timer Interrupt Enable Register (TIER) .............................................................. 276
11.2.7 Timer Control/Status Register (TCSR) ................................................................ 278
11.2.8 Timer Control Register (TCR) ............................................................................. 282
11.2.9 Timer Output Compare Control Register (TOCR) .............................................. 284
11.2.10 Module Stop Control Register (MSTPCR) .......................................................... 286
11.3.1 FRC Increment Timing ........................................................................................ 287
11.3.2 Output Compare Output Timing .......................................................................... 288
11.3.3 FRC Clear Timing................................................................................................ 289
11.3.4 Input Capture Input Timing ................................................................................. 289
11.3.5 Timing of Input Capture Flag (ICF) Setting ........................................................ 292
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................ 293
Correspondence between PWM Data Register Contents
and Output Waveform.......................................................................................... 251
........................................................................................... 253
......................................................................... 269
Rev. 4.00 Jun 06, 2006 page xxiii of liv
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