DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 751

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.6
24.6.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
24.6.2
Software standby mode is cleared by an external interrupt (NMI pin, or pin IRQ0, IRQ1, IRQ2,
IRQ6, or IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt request
signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in
SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and
interrupt exception handling is started.
Software standby mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if
the corresponding enable bit has been cleared to 0 or has been masked by the CPU.
Clearing with the RES
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
Clearing with the STBY
standby mode.
Software Standby Mode
Clearing Software Standby Mode
Software Standby Mode
RES Pin: When the RES pin is driven low, clock oscillation is started. At the
RES
RES
STBY
STBY
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
Rev. 4.00 Jun 06, 2006 page 695 of 1004
Section 24 Power-Down State
REJ09B0301-0400