DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 169

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.3
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts.
5.3.1
There are nine external interrupt sources from 17 input pins (15 actual pins): NMI, IRQ7 to IRQ0,
and KIN7 to KIN0. KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6 ,
and IRQ2 to IRQ0 can be used to restore the H8S/2138 Group or H8S/2134 Group chip from
software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The
NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a
falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
The interrupt control level can be set with ICR.
The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
Interrupt Sources
External Interrupts
Rev. 4.00 Jun 06, 2006 page 113 of 1004
Section 5 Interrupt Controller
REJ09B0301-0400

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