DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 698

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 ROM
Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the chip measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the
host’s transfer bit rate should be set to (4800, 9600, or 19200) bps.
Table 22.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the chip’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 22.7 System Clock Frequencies for which Automatic Adjustment of the Chip's Bit
Host Bit Rate
19200 bps
9600 bps
4800 bps
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 1920-byte area from
H'(FF)E880 to H'(FF) EFFF and the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for
use by the boot program, as shown in figure 22.10. The area to which the programming control
program is transferred is H'(FF)E080 to H'(FF)E87F (2048 bytes). However, the 8-byte area from
H'(FF)E080 to H'(FF)E087 is reserved for ID codes as shown in figure 22.10. The boot program
Rev. 4.00 Jun 06, 2006 page 642 of 1004
REJ09B0301-0400
Rate Is Possible
(H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
Start
bit
Figure 22.9 Automatic SCI Bit Rate Adjustment
D0
System Clock Frequency for which Automatic Adjustment
of Bit Rate Is Possible
8 MHz to 20 MHz
4 MHz to 20 MHz
2 MHz to 18 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit