DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 564

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
Table 16.7 Permissible SCL Rise Time (t
IICX
0
1
Rev. 4.00 Jun 06, 2006 page 508 of 1004
REJ09B0301-0400
The I
and 300 ns. The I
table 16.6. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
t
Indication
7.5t
17.5t
cyc
fails to meet the I
in high-speed mode and t
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
2
C Bus Interface [H8S/2138 Group Option]
Normal mode
High-speed
mode
Normal mode
High-speed
mode
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
I
Specification
(Max.)
1000 ns
300 ns
1000 ns
300 ns
2
C Bus
in standard mode fail to satisfy the I
Sr
) Values
Sr
/t
5 MHz
1000 ns 937 ns
300 ns
1000 ns 1000 ns 1000 ns 1000 ns 875 ns
300 ns
Time Indication
Sf
=
. Possible solutions that should be investigated
8 MHz
300 ns
300 ns
=
2
C bus interface specifications may
10 MHz
750 ns
300 ns
300 ns
=
2
C bus.
2
C bus interface
2
16 MHz
468 ns
300 ns
300 ns
C bus.
=
cyc
, as shown in
20 MHz
375 ns
300 ns
300 ns
=