DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 506

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.4
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Table 15.13 SCI Interrupt Sources
Channel
0
1
2
Note:
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
Rev. 4.00 Jun 06, 2006 page 450 of 1004
REJ09B0301-0400
* The table shows the initial state immediately after a reset. Relative channel priorities
SCI Interrupts
can be changed by the interrupt controller.
Interrupt
Source
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
Description
Receive error (ORER, FER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
Receive error (ORER, PER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
Receive error (ORER, PER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
DTC Activation
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Priority *
High
Low