DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 543

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 16.4 I
16.3.2
In I
data, and the slave device returns an acknowlede signal.
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR write operations, are described below.
[1] Set the ICE bit in ICCR to l. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
[2] Read the BBSY flag to confirm that the bus is free.
[3] Set the MST and TRS bits to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP. This switches SDA from high to low when SCL is high, and
[5] When the start condition is generated, the IRIC and IRTR flags are set to 1. If the IEIC bit in
[6] Write data to ICDR (slave address + R/W)
Legend
S
SLA
R/W
A
DATA
P
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
in STCR, according to the operation mode.
generates the start condition.
ICCR has been set to l, an interrupt request is sent to the CPU.
With the I
data following the start condition indicates the 7-bit slave address and transmit/receive
direction.
Then clear the IRIC flag to indicate the end of transfer.
Master Transmit Operation
Start condition. The master device drives SDA from high to low while SCL is high
Slave address, by which the master device selects a slave device
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
Stop condition. The master device drives SDA from low to high while SCL is high
2
2
C Bus Data Format Symbols
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame
Section 16 I
Rev. 4.00 Jun 06, 2006 page 487 of 1004
2
C Bus Interface [H8S/2138 Group Option]
REJ09B0301-0400