DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 259
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 259 of 1063
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8.3.2
Table 8.5 shows the port 2 register configuration.
Table 8.5
Note:
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
Name
Port 2 data direction register
Port 2 data register
Port 2 MOS pull-up control
register
Bit
Initial value
Read/Write
Mode 1
The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
Modes 2 and 3 (EXPE = 1)
The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set
to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output
ports by setting the IOSE bit to 1.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
* Lower 16 bits of the address.
Register Configuration
Port 2 Registers
P27DDR
W
7
0
P26DDR
W
6
0
Abbreviation
P2DDR
P2DR
P2PCR
P25DDR
W
5
0
P24DDR
W
4
0
R/W
W
R/W
R/W
Rev. 4.00 Jun 06, 2006 page 203 of 1004
P23DDR
W
3
0
Initial Value
H'00
H'00
H'00
P22DDR
W
2
0
P21DDR
Section 8 I/O Ports
REJ09B0301-0400
W
1
0
Address *
H'FFB1
H'FFB3
H'FFAD
P20DDR
W
0
0
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