DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 563
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 16.6 I
Note:
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Electrical Characteristics. Note that the I
met with a system clock frequency of less than 5 MHz.
The I
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
* 6t
2
C bus interface specification for the SCL rise time t
cyc
2
C Bus Timing (SCL and SDA Output)
when IICX is 0, 12t
cyc
when 1.
2
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
Section 16 I
2
C bus interface AC timing specifications will not be
sr
(the time for SCL to go from low to V
cyc
2
C bus interface, the high period of SCL is
, as shown in I
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
Rev. 4.00 Jun 06, 2006 page 507 of 1004
cyc
2
SCLO
SCLO
SCLO
SCLO
SCLO
C Bus Interface [H8S/2138 Group Option]
– (6t
to 256t
– 3t
– 1t
– 1t
+ 2t
sr
is under 1000 ns (300 ns for high-
cyc
cyc
cyc
cyc
cyc
2
or 12t
cyc
C bus Timing in section 25,
cyc
* )
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
REJ09B0301-0400
Notes
Figure 25.26
(reference)
IH
) exceeds
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