DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 597

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4
17.4.1
The host interface can issue two interrupt requests to the slave CPU: IBF1 and IBF2. They are
input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is
enabled when the corresponding enable bit is set.
Table 17.10 Input Buffer Full Interrupts
17.4.2
In slave mode (single-chip mode, with HI12E = 1 in SYSCR2), bits P45DR to P43DR in the port
4 data register (P4DR) can be used as host interrupt request latches.
These three P4DR bits are cleared to 0 by the host processor’s read signal (IOR). If CS1 and HA0
are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If
CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To
generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In
processing the interrupt, the host’s interrupt handling routine reads the output data register (ODR1
or ODR2), and this clears the host interrupt latch to 0.
Table 17.11 indicates how these bits are set and cleared. Figure 17.3 shows the processing in
flowchart form.
Table 17.11 HIRQ Setting/Clearing Conditions
Interrupt
IBF1
IBF2
Host Interrupt
Signal
HIRQ11 (P43)
HIRQ1 (P44)
HIRQ12 (P45)
Interrupts
IBF1, IBF2
HIRQ11, HIRQ1, and HIRQ12
Description
Requested when IBFIE1 is set to 1 and IDR1 is full
Requested when IBFIE2 is set to 1 and IDR2 is full
Setting Condition
Slave CPU reads 0 from bit P43DR,
then writes 1
Slave CPU reads 0 from bit P44DR,
then writes 1
Slave CPU reads 0 from bit P45DR,
then writes 1
Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 541 of 1004
Clearing Condition
Slave CPU writes 0 in bit P43DR, or
host reads output data register 2
Slave CPU writes 0 in bit P44DR, or
host reads output data register 1
Slave CPU writes 0 in bit P45DR, or
host reads output data register 1
REJ09B0301-0400