DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 338
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 338 of 1063
- Download datasheet (6Mb)
Section 11 16-Bit Free-Running Timer
11.2.8
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Bit 7
IEDGA
0
1
Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B
signal (FTIB).
Bit 6
IEDGB
0
1
Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC
0
1
Rev. 4.00 Jun 06, 2006 page 282 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
Timer Control Register (TCR)
Description
Capture on the falling edge of FTIA
Capture on the rising edge of FTIA
Description
Capture on the falling edge of FTIB
Capture on the rising edge of FTIB
Description
Capture on the falling edge of FTIC
Capture on the rising edge of FTIC
IEDGA
R/W
7
0
IEDGB
R/W
6
0
IEDGC
R/W
5
0
IEDGD
R/W
4
0
BUFEA
R/W
3
0
BUFEB
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0
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