DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 118
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 118 of 1063
- Download datasheet (6Mb)
Section 2 CPU
2.8
2.8.1
The CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Rev. 4.00 Jun 06, 2006 page 62 of 1004
REJ09B0301-0400
Note: * The power-down state also includes a medium-speed mode, module stop mode,
Processing
states
Processing States
Overview
sub-active mode, sub-sleep mode, and watch mode.
Exception-handling
Program execution
Bus-released state
Power-down state
Figure 2.14 Processing States
The CPU and all on-chip supporting modules have been
initialized and are stopped.
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
The CPU executes program instructions in sequence.
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
CPU operation is stopped
to conserve power.*
Reset state
state
state
Hardware standby
Software standby
Sleep mode
mode
mode
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