DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 586

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
Bit 0—Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using
firmware to manipulate the P81 output.
Bit 0
FGA20E
0
1
17.2.4
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CS1 is low, information on the host data bus is written into IDR1 at the
rising edge of IOW. The HA0 state is also latched into the C/D bit in STR1 to indicate whether the
written information is a command or data.
The initial values of IDR1 after a reset and in standby mode are undetermined.
17.2.5
ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODR1 contents are output on the host data bus when HA0 is low, CS1
is low, and IOR is low.
The initial values of ODR1 after a reset and in standby mode are undetermined.
Rev. 4.00 Jun 06, 2006 page 530 of 1004
REJ09B0301-0400
Bit
Initial value
Slave Read/Write
Host Read/Write
Bit
Initial value
Slave Read/Write
Host Read/Write
Input Data Register 1 (IDR1)
Output Data Register 1 (ODR1)
Description
Fast A20 gate function is disabled
Fast A20 gate function is enabled
ODR7
IDR7
R/W
—
W
—
R
R
7
7
ODR6
IDR6
R/W
—
—
W
R
R
6
6
ODR5
IDR5
R/W
—
W
—
R
R
5
5
ODR4
IDR4
R/W
—
—
W
R
R
4
4
ODR3
IDR3
R/W
—
W
—
R
R
3
3
ODR2
IDR2
R/W
—
W
—
R
R
2
2
ODR1
IDR1
R/W
—
W
—
R
R
1
1
(Initial value)
ODR0
IDR0
R/W
—
—
W
R
R
0
0