DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 584

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
17.2.2
SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface
functions are enabled or disabled by the HI12E bit in SYSCR2. SYSCR2 is initialized to H'00 by a
reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be
set and changed by software. For details see section 8, I/O Ports.
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see
section 8, I/O Ports.
Bit 4—Reserved: Do not write 1 to this bit.
Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function.
When this function is enabled, host interface pin functions can be halted, and the pins placed in the
high-impedance state, according to the state of the HIFSD pin.
Bit 3
SDE
0
1
Bit 2—CS4 Enable (CS4E): Reserved. Do not write 1 to this bit.
Bit 1—CS3 Enable (CS3E): Reserved. Do not write 1 to this bit.
Bit 0—Host Interface Enable Bit (HI12E): Enables or disables host interface functions in
single-chip mode. When the host interface functions are enabled, slave mode is entered and
processing is performed for data transfer between the slave and host.
Rev. 4.00 Jun 06, 2006 page 528 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
System Control Register 2 (SYSCR2)
Description
Host interface pin shutdown function disabled
Host interface pin shutdown function enabled
KWUL1
R/W
7
0
KWUL0
R/W
6
0
P6PUE
R/W
5
0
—
—
4
0
SDE
R/W
3
0
CS4E
R/W
2
0
CS3E
R/W
1
0
(Initial value)
HI12E
R/W
0
0