DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 385

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.5
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer
mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare-
match count mode). In this case, the timer operates as described below.
16-Bit Count Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a
single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8
bits.
Compare-Match Count Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts
compare-match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
Usage Note: If the 16-bit count mode and compare-match count mode are set simultaneously, the
input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop
operating. Simultaneous setting of these two modes should therefore be avoided.
Setting of compare-match flags
Counter clear specification
Pin output
The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear
by the TMRI0 pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot
be cleared independently.
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with
the 16-bit compare-match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with
the lower 8-bit compare-match conditions.
Operation with Cascaded Connection
Rev. 4.00 Jun 06, 2006 page 329 of 1004
Section 12 8-Bit Timers
REJ09B0301-0400