DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 99

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number

DF2134AFA20V

Description

IC H8S/2100 MCU FLASH 80QFP

Manufacturer

Renesas Electronics America

Series

H8® H8S/2100r

Datasheets

1.HEWH8E10A.pdf (19 pages)

2.D12312SVTE25V.pdf (341 pages)

3.DF2134AFA20V.pdf (1063 pages)

Specifications of DF2134AFA20V

Core Processor

H8S/2000

Core Size

16-Bit

Speed

20MHz

Connectivity

IrDA, SCI

Peripherals

POR, PWM, WDT

Number Of I /o

58

Program Memory Size

128KB (128K x 8)

Program Memory Type

FLASH

Ram Size

4K x 8

Voltage - Supply (vcc/vdd)

4 V ~ 5.5 V

Data Converters

A/D 8x10b; D/A 2x8b

Oscillator Type

Internal

Operating Temperature

-20°C ~ 75°C

Package / Case

80-QFP

For Use With

3DK2166 - DEV EVAL KIT H8S/2166

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

DF2134AFA20V

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Current page: 99 of 1063
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2.6.2

Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU

can use.

Table 2.2

Legend: B: Byte

Notes:

Data

transfer

Arithmetic

operations

Logic

operations

Shift

Bit manipulation

Branch

System

control

Block data transfer

Function

W: Word

L:

1.

2.

3.

Instructions and Addressing Modes

MOV

POP, PUSH

LDM *

MOVFPE *

MOVTPE *

ADD, CMP

SUB

ADDX, SUBX

ADDS, SUBS

INC, DEC

DAA, DAS

MULXU, DIVXU

MULXS, DIVXS

NEG

EXTU, EXTS

TAS *

AND, OR, XOR

NOT

Bcc, BSR

JMP, JSR

RTS

TRAPA

RTE

SLEEP

LDC

STC

ANDC, ORC,

XORC

NOP

Longword

Cannot be used in the H8S/2138 Group or H8S/2134 Group.

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

Instruction

Combinations of Instructions and Addressing Modes

2

3

, STM *

1

1

,

3

BWL BWL BWL BWL BWL BWL

BWL BWL

BWL BWL

WL

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B

B

B

BWL

BWL

BWL

BWL

BWL

BW

BW

WL

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B

B

B

B

B

L

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W

W

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B

B

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W

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W

W

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W

W

Addressing Modes

Rev. 4.00 Jun 06, 2006 page 43 of 1004

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B

B

BWL

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W

W

B

B

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BWL

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W

W

B

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REJ09B0301-0400

Section 2 CPU

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BW

WL

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L

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