DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 595
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 595 of 1063
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Table 17.8 Fast A20 Gate Output Signals
Notes: 1. Arbitrary data with bit 1 set to 1.
17.3.4
Host interface output can be placed in the high-impedance state according to the state of the
HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enables the HIFSD pin is slave mode.
The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface
output pins (HIRQ1, HIRQ11, HIRQ12, and GA20) in the high-impedance state. At the same
time, the host interface input pins (CS1, CS2 or ECS2, IOW, IOR, and HA0) are disabled (fixed at
the high input state internally) regardless of the pin states, and the signals of the multiplexed
HA0
1
0
1
1
0
1
1
0
1/0
1
0
1/0
1
1
1
1
1
0
1
2. Arbitrary data with bit 1 cleared to 0.
Data/Command
H'D1 command
1 data *
H'FF command
H'D1 command
0 data *
H'FF command
H'D1 command
1 data *
Command other than H'FF
and H'D1
H'D1 command
0 data *
Command other than H'FF
and H'D1
H'D1 command
Command other than H'D1
H'D1 command
H'D1 command
H'D1 command
Any data
H'D1 command
Host Interface Pin Shutdown Function
1
2
1
2
Internal CPU
Interrupt Flag (IBF)
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 539 of 1004
GA20
(P81)
Q
1
Q (1)
Q
0
Q (0)
Q
1
Q (1)
Q
0
Q (0)
Q
Q
Q
Q
Q
1/0
Q(1/0)
Remarks
Turn-on sequence
Turn-off sequence
Turn-on sequence
(abbreviated form)
Turn-off sequence
(abbreviated form)
Cancelled sequence
Retriggered sequence
Consecutively executed
sequences
REJ09B0301-0400
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