DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 965
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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LPWRCR—Low-Power Control Register
Bit
Initial value
Read/Write
Direct-transfer on flag
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
0
1
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When a SLEEP instruction is executed in subactive mode, a transition is made to
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When a SLEEP instruction is executed in subactive mode, a transition is made directly
a transition is made to sleep mode, software standby mode, or watch mode*
subsleep mode or watch mode
a transition is made directly to subactive mode * , or a transition is made to sleep mode
or software standby mode
to high-speed mode, or a transition is made to subsleep mode
be set.
DTON
R/W
7
0
Note: * When a transition is made to watch mode or subactive mode,
Low-speed on flag
0
1
• When a SLEEP instruction is executed in high-speed mode or
• When a SLEEP instruction is executed in subactive mode, a transition
• After watch mode is cleared, a transition is made to high-speed mode
• When a SLEEP instruction is executed in high-speed mode a
• When a SLEEP instruction is executed in subactive mode, a transition
• After watch mode is cleared, a transition is made to subactive mode
medium-speed mode, a transition is made to sleep mode, software
standby mode, or watch mode *
is made to watch mode, or directly to high-speed mode
transition is made to watch mode or subactive mode *
is made to subsleep mode or watch mode
LSON
R/W
high-speed mode must be set.
6
0
NESEL
R/W
Noise elimination sampling frequency select
0
1
5
0
Sampling at
Sampling at
EXCLE
R/W
Subclock input enable
4
0
0
1
Subclock input from EXCL pin is disabled
Subclock input from EXCL pin is enabled
Rev. 4.00 Jun 06, 2006 page 909 of 1004
divided by 32
divided by 4
H'FF85
—
—
3
0
Appendix B Internal I/O Registers
—
—
2
0
—
—
1
0
REJ09B0301-0400
—
—
0
0
System
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