DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 365
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 365 of 1063
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Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits
for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access.
(Access is not divided into two 8-bit accesses.)
In the H8S/2138 Group, certain of the channel X and channel Y registers are assigned to the same
address. The TMRX/Y bit in TCONRS determines which register is accessed.
12.2
12.2.1
Each TCNT is an 8-bit readable/writable up-counter.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
access.
TCNT increments on pulses generated from an internal or external clock source. This clock source
is selected by clock select bits CKS2 to CKS0 in TCR.
TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits
CCLR1 and CCLR0 in TCR select the method of clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1.
The timer counters are initialized to H'00 by a reset and in hardware standby mode.
Bit
Initial value
Read/Write
TCNTX, TCNTY
Bit
Initial value
Read/Write
Register Descriptions
Timer Counter (TCNT)
R/W
15
0
R/W
7
0
R/W
14
0
R/W
13
0
R/W
6
0
R/W
12
TCNT0
0
R/W
11
0
R/W
5
0
R/W
10
0
R/W
9
0
R/W
4
0
R/W
8
0
R/W
Rev. 4.00 Jun 06, 2006 page 309 of 1004
7
0
R/W
3
0
R/W
6
0
R/W
5
0
R/W
2
0
R/W
TCNT1
4
0
Section 12 8-Bit Timers
R/W
3
0
R/W
REJ09B0301-0400
1
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
0
0
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