DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 548

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
16.3.4
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
[2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set
[3] When the slave address matches in the first frame following the start condition, the device
[4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
[5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Rev. 4.00 Jun 06, 2006 page 492 of 1004
REJ09B0301-0400
according to the operating mode.
to 1.
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA
is changed from low to high when SCL is high, and the stop condition is detected, the BBSY
flag in ICCR is cleared to 0.
Slave Receive Operation
2
C Bus Interface [H8S/2138 Group Option]