DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 33

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8 Flash Memory Protection.................................................................................................. 651
22.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 654
22.10 Flash Memory Programmer Mode .................................................................................... 655
22.11 Flash Memory Programming and Erasing Precautions..................................................... 667
22.12 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 668
Section 23 Clock Pulse Generator
23.1 Overview........................................................................................................................... 669
23.2 Register Descriptions ........................................................................................................ 670
23.3 Oscillator........................................................................................................................... 672
23.4 Duty Adjustment Circuit................................................................................................... 677
23.5 Medium-Speed Clock Divider .......................................................................................... 677
23.6 Bus Master Clock Selection Circuit .................................................................................. 677
23.7 Subclock Input Circuit ...................................................................................................... 677
23.8 Subclock Waveform Shaping Circuit................................................................................ 678
23.9 Clock Selection Circuit ..................................................................................................... 679
22.7.1 Program Mode ..................................................................................................... 646
22.7.2 Program-Verify Mode.......................................................................................... 647
22.7.3 Erase Mode .......................................................................................................... 649
22.7.4 Erase-Verify Mode .............................................................................................. 649
22.8.1 Hardware Protection ............................................................................................ 651
22.8.2 Software Protection.............................................................................................. 651
22.8.3 Error Protection.................................................................................................... 652
22.10.1 Programmer Mode Setting ................................................................................... 655
22.10.2 Socket Adapters and Memory Map ..................................................................... 656
22.10.3 Programmer Mode Operation .............................................................................. 656
22.10.4 Memory Read Mode ............................................................................................ 657
22.10.5 Auto-Program Mode ............................................................................................ 661
22.10.6 Auto-Erase Mode................................................................................................. 663
22.10.7 Status Read Mode ................................................................................................ 664
22.10.8 Status Polling ....................................................................................................... 666
22.10.9 Programmer Mode Transition Time .................................................................... 666
22.10.10 Notes on Memory Programming...................................................................... 667
23.1.1 Block Diagram ..................................................................................................... 669
23.1.2 Register Configuration......................................................................................... 670
23.2.1 Standby Control Register (SBYCR) .................................................................... 670
23.2.2 Low-Power Control Register (LPWRCR) ........................................................... 671
23.3.1 Connecting a Crystal Resonator........................................................................... 672
23.3.2 External Clock Input ............................................................................................ 674
.................................................................................. 669
Rev. 4.00 Jun 06, 2006 page xxxi of liv