DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 292

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 I/O Ports
Port 9 Data Register (P9DR)
Note:
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.10.3
Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger
input pin (ADTRG), HIF input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the
subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, WR, WAIT), and the
system clock ( ) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1)
expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions
are shown in table 8.20.
Rev. 4.00 Jun 06, 2006 page 236 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the output pin and
pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the
corresponding pins become input ports.
* Determined by the state of pin P96.
Pin Functions
P97DR
R/W
7
0
P96DR
— *
R
6
P95DR
R/W
5
0
P94DR
R/W
4
0
P93DR
R/W
3
0
P92DR
R/W
2
0
P91DR
R/W
1
0
P90DR
R/W
0
0