DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 456

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2
TEIE
0
1
Note:
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1
CKE1
0
1
Notes: 1. Initial value
Rev. 4.00 Jun 06, 2006 page 400 of 1004
REJ09B0301-0400
* TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Bit 0
CKE0
0
1
0
1
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Description
Transmit-end interrupt (TEI) request disabled *
Transmit-end interrupt (TEI) request enabled *
Description
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Internal clock/SCK pin functions as I/O port *
Internal clock/SCK pin functions as serial clock
output *
Internal clock/SCK pin functions as clock output *
Internal clock/SCK pin functions as serial clock
output
External clock/SCK pin functions as clock input *
External clock/SCK pin functions as serial clock
input
External clock/SCK pin functions as clock input *
External clock/SCK pin functions as serial clock
input
1
(Initial value)
1
3
3
2

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