DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 150

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 4 Exception Handling
4.2
4.2.1
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling begins when the RES pin changes from low to high.
H8S/2138 Group and H8S/2134 Group MCUs can also be reset by overflow of the watchdog
timer. For details, see section 14, Watchdog Timer (WDT).
4.2.2
The MCU enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms when powering on. To
reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset,
see appendix D.1, Port States in Each Processing State.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
[1] The internal state of the CPU and the registers of the on-chip supporting modules are
[2] The reset exception vector address is read and transferred to the PC, and program execution
Figures 4.2 and 4.3 show examples of the reset sequence.
Rev. 4.00 Jun 06, 2006 page 94 of 1004
REJ09B0301-0400
initialized, and the I bit is set to 1 in CCR.
starts from the address indicated by the PC.
Reset
Overview
Reset Sequence

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