DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 37

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Figure 2.14
Figure 2.15
Figure 2.16
Figure 2.17
Figure 2.18
Figure 2.19
Figure 2.20
Section 3 MCU Operating Modes
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Section 4 Exception Handling
Figure 4.1
Internal Block Diagram of H8S/2138 Group.....................................................
Internal Block Diagram of H8S/2134 Group.....................................................
Pin Arrangement of H8S/2138 Group (FP-80A, TFP-80C: Top View) ............
Pin Arrangement of H8S/2134 Group (FP-80A, TFP-80C: Top View) ............ 10
CPU Operating Modes....................................................................................... 28
Exception Vector Table (Normal Mode) ........................................................... 29
Stack Structure in Normal Mode ....................................................................... 30
Exception Vector Table (Advanced Mode) ....................................................... 31
Stack Structure in Advanced Mode ................................................................... 32
Memory Map ..................................................................................................... 33
CPU Registers ................................................................................................... 34
Usage of General Registers ............................................................................... 35
Stack .................................................................................................................. 36
General Register Data Formats.......................................................................... 39
Memory Data Formats....................................................................................... 41
Instruction Formats (Examples) ........................................................................ 54
Branch Address Specification in Memory Indirect Mode ................................. 57
Processing States ............................................................................................... 62
State Transitions ................................................................................................ 63
Stack Structure after Exception Handling (Examples) ...................................... 65
On-Chip Memory Access Cycle........................................................................ 67
Pin States during On-Chip Memory Access ...................................................... 67
On-Chip Supporting Module Access Cycle....................................................... 68
Pin States during On-Chip Supporting Module Access..................................... 69
H8S/2138 (Except for F-ZTAT A-Mask Version) and H8S/2134 Memory Map
in Each Operating Mode.................................................................................... 80
H8S/2138 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
H8S/2133 Memory Map in Each Operating Mode............................................ 84
H8S/2137 and H8S/2132 Memory Map in Each Operating Mode.................... 86
H8S/2130 Memory Map in Each Operating Mode............................................ 88
Exception Sources ............................................................................................. 92
Figures
Rev. 4.00 Jun 06, 2006 page xxxv of liv
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