DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 591

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 17.4 Set/Clear Timing for STR2 Flags
Note:
17.2.10 Module Stop Control Register (MSTPCR)
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.
Flag
C/D
IBF *
OBF
MSTPCRL
Bit 2
MSTP2
0
1
Bit
Initial value
Read/Write
* The IBF flag setting and clearing conditions are different when the fast A20 gate is
used. For details see table 17.8, Fast A20 Gate Output Signals.
Setting Condition
Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal
(IOW) when writing to IDR2
Falling edge of slave’s internal write
signal (WR) when writing to ODR2
Description
Host interface module stop mode is cleared
Host interface module stop mode is set
MSTP15
R/W
7
0
MSTP14
R/W
6
0
MSTP13
R/W
5
1
MSTPCRH
MSTP12
R/W
4
1
MSTP11
R/W
3
1
MSTP10
R/W
2
1
MSTP9
R/W
1
1
MSTP8
R/W
Clearing Condition
Rising edge of host’s write signal (IOW) when
HA0 is low
Falling edge of slave’s internal read signal
(RD) when reading IDR2
Rising edge of host’s read signal (IOR) when
reading ODR2
0
1
Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 535 of 1004
MSTP7
R/W
7
1
MSTP6
R/W
6
1
MSTP5
R/W
5
1
MSTPCRL
MSTP4
R/W
4
1
MSTP3
R/W
3
1
REJ09B0301-0400
MSTP2
R/W
2
1
(Initial value)
MSTP1
R/W
1
1
MSTP0
R/W
0
1