DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 191
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 191 of 1063
- Download datasheet (6Mb)
5.7.3
The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt
request with the DTCE bit of DTCERA to DTCERE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC performs the specified number of data transfers and the transfer counter reaches 0,
following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the
CPU.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,
for the respective priorities.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.10 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB
in the DTC.
Table 5.10 Interrupt Source Selection and Clearing Control
Legend:
O: The relevant interrupt is used. The interrupt source is not cleared.
*:
DTCE
0
1
: The relevant interrupt is used. Interrupt source clearing is performed.
: The relevant bit cannot be used.
(The CPU should clear the source flag in the interrupt handling routine.)
Don’t care
Operation
Settings
DTC
DISEL
*
0
1
Interrupt Source Selection/Clearing Control
DTC
O
Rev. 4.00 Jun 06, 2006 page 135 of 1004
Section 5 Interrupt Controller
CPU
REJ09B0301-0400
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