DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 16

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 4.00 Jun 06, 2006 page xiv of liv
B.3 Function
Item
938
939
Page
STCR H'FFC3 System
Figure amended
Bit
Initial value
Read/Write
SYSCR H'FFC4 System
Figure amended
Bit
Initial value
Read/Write
Revision (See Manual for Details)
Reserved
CS2E
R/W
R/W
—
7
0
7
0
IICX1
IOSE
R/W
R/W
6
0
6
0
I
2
C transfer select 1 and 0 *
Interrupt control selection mode 1 and 0
INTM1
INTM1
IICX0
Bit 5
R/W
0
1
R
5
0
I
5
0
2
0
1
C master enable
INTM0
Bit 4
CPU access to SCI0, SCI1, and SCI2 control
registers is enabled
CPU access to I
registers and control registers is enabled
0
1
0
1
INTM0
IICE
R/W
R/W
4
0
External reset
Flash memory control register enable
4
0
control mode
0
1
0
1
Interrupt
Reset generated by watchdog timer overflow
Reset generated by an external reset
Flash memory control register not selected
Flash memory control register selected
0
1
2
3
NMI edge select
0
1
FLSHE
XRST
R/W
3
0
R
2
3
1
Falling edge
Rising edge
2
C bus interface data, PWMX data
Interrupts controlled by I bit
Interrupts controlled by I and UI bits, and ICR
Cannot be used in the LSI
Cannot be used in the LSI
Host interface enable
0
1
Reserved
NMIEG
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
R/W
R/W
—
2
0
2
0
RAM Enable
0
1
Internal Clock Source
Select 1 and 0 *
Description
ICKS1
On-chip RAM is disabled
On-chip RAM is enabled
R/W
R/W
HIE
1
1
0
0
ICKS0
RAME
(Initial value)
R/W
R/W
0
0
1
0
1