DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 485
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 485 of 1063
- Download datasheet (6Mb)
Table 15.11 Receive Errors and Conditions for Occurrence
Figure 15.8 shows an example of the operation for reception in asynchronous mode.
Receive Error
Overrun error
Framing error
Parity error
RDRF
FER
1
Start
bit
0
D0
Abbreviation
ORER
FER
PER
Figure 15.8 Example of SCI Operation in Reception
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
1 frame
Data
D7
Occurrence Condition
When the next data reception is
completed while the RDRF flag
in SSR is set to 1
When the stop bit is 0
When the received data differs
from the parity (even or odd) set
in SMR
RXI interrupt
request
generated
Parity
bit
0/1
Section 15 Serial Communication Interface (SCI, IrDA)
Stop
bit
1
Start
bit
0
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
D0
Rev. 4.00 Jun 06, 2006 page 429 of 1004
D1
Data
Data Transfer
Receive data is not
transferred from RSR to
RDR
Receive data is transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
D7
Parity
bit
ERI interrupt request
generated by framing
error
0/1
REJ09B0301-0400
Stop
bit
0
Idle state
(mark state)
1
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