DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 75
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 75 of 1063
- Download datasheet (6Mb)
Type
Operating
mode
control
System
control
Address
bus
Data bus
Bus control
Symbol
MD1
MD0
RES
STBY
A15 to
A0
D7 to
D0
WAIT
RD
WR
AS/IOS
Pin No.
FP-80A
TFP-80C
4
5
1
7
48 to 55,
57 to 64
72 to 65
13
16
17
15
I/O
Input
Input
Input
Output Address bus: These pins output an address.
Input/
output
Input
Output Read: When this pin is low, it indicates that the
Output Write: When this pin is low, it indicates that the
Output Address strobe: When this pin is low, it indicates
Name and Function
Mode pins: These pins set the operating mode.
The relation between the settings of pins MD1 and
MD0 and the operating mode is shown below.
These pins should not be changed while the MCU
is operating.
MD1 MD0
0
1
1
Reset input: When this pin is driven low, the chip is
reset.
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
Data bus (upper): Bidirectional data bus.
Used for 8-bit data.
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address
space.
external address space is being read.
external address space is being written to.
that address output on the address bus is valid.
1
0
1
Rev. 4.00 Jun 06, 2006 page 19 of 1004
Operating
Mode
Mode 1
Mode 2
Mode 3
Description
Normal
Advanced
Normal
Expanded mode with
on-chip ROM disabled
Expanded mode with
on-chip ROM enabled
or single-chip mode
Expanded mode with
on-chip ROM enabled
or single-chip mode
Section 1 Overview
REJ09B0301-0400
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