DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 197

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 2—Reserved: Do not write 0 to this bit.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.
6.2.2
WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access
states, wait mode, and number of wait states for external memory space. The on-chip memory and
internal I/O register bus width and number of access states are fixed, irrespective of the WSCR
settings.
WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4
BRSTS1
0
1
Bit 3
BRSTS0
0
1
Bit
Initial value
Read/Write
Wait State Control Register (WSCR)
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
Description
Max. 4 words in burst access
Max. 8 words in burst access
RAMS
R/W
7
0
RAM0
R/W
6
0
ABW
R/W
5
1
AST
R/W
4
1
Rev. 4.00 Jun 06, 2006 page 141 of 1004
WMS1
R/W
3
0
WMS0
R/W
2
0
Section 6 Bus Controller
WC1
R/W
REJ09B0301-0400
1
1
(Initial value)
(Initial value)
WC0
R/W
0
1